View MAX3881ECBTD_4365709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max3881 deserializer with clock recovery is ideal for converting 2.488gbps serial data to 16-bit-wide, 155mbps parallel data for sdh/sonet applications. operating from a single +3.3v supply, this device accepts high-speed serial-data inputs and delivers sin- gle-ended pecl parallel data outputs and a differential pecl parallel clock output for interfacing with digital circuitry. the max3881 includes a low-power clock recovery and data retiming function for 2.488gbps applications. the fully integrated phase-locked loop (pll) recovers a synchronous clock signal from the serial nrz data input; the signal is then retimed by the recovered clock. the max3881? jitter performance exceeds all sdh/sonet specifications. an additional 2.488gbps serial input is available for system loopback diagnostic testing. the device also includes a ttl-compatible loss-of-lock ( lol ) monitor. the max3881 is available in the extended temperature range (-40? to +85?) in a 64-pin tqfp-ep package. applications 2.488gbps sdh/sonet transmission systems add/drop multiplexers digital cross-connects features single +3.3v supply 530mw operating power fully integrated clock recovery and data retiming exceeds ansi, itu, and bellcore specifications additional high-speed input facilitates system loopback diagnostic testing 2.488gbps serial to 155mbps parallel conversion differential pecl clock output single-ended pecl data outputs tolerates >2000 consecutive identical digits loss-of-lock indicator max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery ________________________________________________________________ maxim integrated products 1 19-1996; rev 1; 12/01 part max3881ecb -40? to +85? temp. range pin-package 64 tqfp-ep* ordering information * exposed pad evaluation kit available pin configuration v cc pd13 v cc gnd v cc pd14 gnd v cc pd11 v cc pd12 v cc pd15 gnd lol gnd slbi+ v cc sdi- sdi+ v cc phadj- gnd gnd sis v cc slbi- phadj+ v cc fil- fil+ gnd pclk+ pclk- v cc pd0 v cc pd1 v cc gnd v cc pd2 v cc pd3 v cc pd4 v cc gnd pd10 top view v cc pd9 v cc pd8 v cc gnd v cc pd7 v cc pd6 v cc pd5 v cc gnd v cc tqfp-ep* 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 52 53 49 50 51 33 34 35 36 37 48 64 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max3881 *exposed pad is connected to gnd. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical application circuit appears at end of data sheet.
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, pecl loads = 50 ? to (v cc - 2v), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. positive supply voltage (v cc )...............................-0.5v to +7.0v input voltage level (sdi+, sdi-, slbi+, slbi-) ...............................(v cc - 0.5v) to (v cc + 0.5v) input current level (sdi+, sdi-, slbi+, slbi-)................?0ma voltage at lol , sis, phadj+, phadj-, fil+, fil- .................................................-0.5v to (v cc + 0.5v) pecl output current ..........................................................50ma continuous power dissipation (t a = +85?) 64-pin tqfp (derate 33.3mw/? above +85?)............1.44w operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? figure 1 excluding pecl outputs figure 2 t a = 0? to +85? conditions mvp-p 50 800 v id differential input voltage ma 160 240 i cc supply current v v cc - 0.4 v cc + 0.2 v is single-ended input voltage ? 50 r in input termination to v cc v cc - v cc - 1.025 0.88 units min typ max symbol parameter v 0.8 v il input low voltage v 2.0 v ih input high voltage i oh 40? v 2.4 v cc v oh output high voltage ? -10 +10 input current i ol 1ma v 0.4 v ol output low voltage t a = -40? to 0? v v cc - v cc - 1.085 0.88 v oh pecl output high voltage t a = 0? to +85? v cc - v cc - 1.81 1.62 t a = -40? to 0? v v cc - v cc - 1.83 1.555 v ol pecl output low voltage serial data inputs (sdi, slbi) pecl outputs (pd _ , pclk) ttl inputs and outputs (sis, lol )
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = +3.0v to +3.6v, pecl loads = 50 ? to (v cc - 2v), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) (note 1) note 1: ac characteristics are guaranteed by design and characterization. note 2: at jitter frequencies <70khz, the jitter tolerance of the max3881 outperforms the itu/bellcore specifications. figure 2 100khz to 2.5ghz f = 10mhz f = 70khz (note 2) f = 100khz f = 1mhz 2.5ghz to 4.0ghz conditions db -11 input return loss (sdi? slbi? ps 200 450 900 t clk-q parallel clock-to-data output delay mbps 155.52 gbps 2.488 sdi serial data rate parallel output data rate -18 bits >2,000 tolerated consecutive identical digits uip-p 0.28 0.46 jitter tolerance 2.31 3.3 1.74 2.41 0.38 0.57 units min typ max symbol parameter sdi+ sdi- v id (sdi+) - (sdi-) 50mvp-p min 800mvp-p max 25mv min 400mv max figure 1. input amplitude pclk pd0?d15 t clk-q figure 2. timing parameters 20% to 80% output edge speed 800 t r , t f ps
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 4 _______________________________________________________________________________________ 1 0.1 10 100 1000 jitter tolerance vs. input voltage 0.3 0.2 max3881 toc04 input voltage (mvp-p) jitter tolernce (uip-p) 0.5 0.4 0.7 0.8 0.6 0.9 0 sonet spec jitter frequency = 5mhz jitter frequency = 1mhz 10 -10 10 -8 10 -9 10 -6 10 -7 10 -4 10 -5 10 -3 8.0 8.5 9.0 9.5 10 bit error ratio vs. input voltage max3881-05 input voltage (mvp-p) bit error ratio 200 300 400 600 500 700 -50 0 -25 25 50 75 100 parallel clock to data output propagation delay vs. temperature max3881-06 temperature ( c) pclk to data output propagation delay (ps) typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 1.64ns/div data clock recovered data and clock max3881-01 2 23 - 1 pattern 140 150 160 170 180 190 200 -50 -25 0 25 50 75 100 supply current vs. temperature max3881-02 temperature ( c) supply current (ma) v cc = +3.6v v cc = +3.0v 10.0 0.1 1,000 10,000 1.0 jitter frequency (khz) input jitter (uip-p) 100 10 jitter tolerance max3881 toc03 c f = 0.1 f c f = 1.0 f
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 5 name function 1, 15, 16, 17, 25, 33, 41, 49, 57, 62, 64 gnd ground pin pin description 2 fil+ positive filter input. pll loop filter connection. connect a 1.0? capacitor between fil+ and fil-. 3 fil- negative filter input. pll loop filter connection. connect a 1.0? capacitor between fil+ and fil-. 4, 7, 10, 13, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60 v cc +3.3v supply voltage 5 phadj+ positive phase-adjust input. used to optimally align internal pll phase. connect to v cc if not used. 6 phadj- negative phase-adjust input. used to optimally align internal pll phase. connect to v cc if not used. 8 sdi+ positive serial data input. 2.488gbps data stream. 9 sdi- negative serial data input. 2.488gbps data stream. 11 slbi+ positive system loopback input. 2.488gbps data stream. 12 slbi- negative system loopback input. 2.488gbps data stream. 14 sis signal input selection. ttl low for normal data input (sdi). ttl high for system loopback input (slbi). 18 pclk+ positive parallel clock pecl output 19 pclk- negative parallel clock pecl output 21, 23, 27, 29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 pd0 to pd15 parallel data single-ended pecl outputs. data is updated on the negative transition of the pclk signal (figure 2). 63 lol loss-of-lock output. pll loss-of-lock monitor, ttl active low (internal 10k ? pullup resistor). the lol monitor is valid only when a data stream is present on the inputs to the max3881. ep exposed pad ground. this must be soldered to a circuit board for proper electrical and thermal performance (see package information ).
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 6 _______________________________________________________________________________________ detailed description the max3881 deserializer with clock recovery converts 2.488gbps serial data to 16-bit-wide, 155mbps parallel data. the device combines a fully integrated phase- locked loop (pll), input amplifier, data retiming block, 16-bit demultiplexer, clock divider, and pecl output buffer (figure 3). the pll consists of a phase/frequen- cy detector (pfd), a loop filter, and a voltage-controlled oscillator (vco). the max3881 is designed to deliver the best combination of jitter performance and power dissipation by using a differential signal architecture and low-noise design techniques. the pll recovers the serial clock from the serial input data stream. the demultiplexer generates a 16-bit-wide 155mbps paral- lel data output. input amplifier the input amplifiers on both the main data and system loopback accept a differential input amplitude from 50mvp-p to 800mvp-p. the bit error ratio (ber) is bet- ter than 1 x 10 -10 for input signals as small as 9.5mvp-p, figure 3. max3881 functional diagram max3881 sdi+ amp pecl lol 50 ? 50 ? mux phase & frequency detector sdi- slbi+ amp slbi- sis v cc v cc loop filter vco 16-bit demultiplexer d q ck phadj+ phadj- fil+ fil- clock divider pclk+ pclk- pd15 pecl pd1 pecl pd0 pecl ttl 0 i 0 i
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 7 although the jitter tolerance performance will be degraded. for interfacing with pecl signal levels, see applications information . phase detector the phase detector in the max3881 produces a volt- age proportional to the phase difference between the incoming data and the internal clock. because of its feedback nature, the pll drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. the external phase adjust pins (phadj+, phadj-) allow the user to vary the internal phase alignment. frequency detector the digital frequency detector (fd) aids frequency acquisition during start-up conditions. the frequency difference between the received data and the vco clock is derived by sampling the in-phase and quadra- ture vco outputs on both edges of the data input sig- nal. depending on the polarity of the frequency difference, the fd drives the vco until the frequency difference is reduced to zero. once frequency acquisi- tion is complete, the fd returns to a neutral state. false locking is completely eliminated by this digital frequen- cy detector. loop filter and vco the phase detector and frequency detector outputs are summed into the loop filter. a 1.0? capacitor, c f , is required to set the pll damping ratio. the loop filter output controls the on-chip lc vco run- ning at 2.488ghz. the vco provides low phase noise and is trimmed to the correct frequency. loss-of-lock monitor a loss-of-lock ( lol ) monitor is included in the max3881 frequency detector. a loss-of-lock condition is signaled with a ttl low. when the pll is frequency- locked, lol switches to ttl high in approximately 800ns. note that the lol monitor is only valid when a data stream is present on the inputs to the max3881. as a result, lol does not detect a loss-of-power condition resulting from a loss of the incoming signal. positive emitter-coupled logic (pecl) outputs the max3881 features pecl outputs for the parallel clock and data outputs. for proper operation, pecl outputs should be terminated with 50 ? to (v cc - 2v). in many cases, it is not feasible to use the 50 ? to (v cc - 2v) termination, so it may be preferable to terminate to the th?venin equivalent. see application note hfan-1, interfacing between cml, pecl, and lvds for more details regarding the th?venin-equivalent pecl termi- nation. design procedure jitter tolerance and input sensitivity trade-offs when the received data amplitude is higher than 50mvp-p, the max3881 provides a typical jitter toler- ance of 0.46uip-p at jitter frequencies greater than 10mhz. the sdh/sonet jitter tolerance specification is 0.15uip-p, leaving a jitter allowance of 0.31uip-p for receiver preamplifier and postamplifier design. the ber is better than 1 x 10 -10 for input signals greater than 9.5mvp-p. at 25mvp-p, jitter tolerance will be degraded, but will still be above the sdh/sonet requirement. trade-offs can be made between jitter tol- erance and input voltage according to the specific application. see the typical operating characteristics for jitter tolerance and ber vs. input voltage graphs. applications information consecutive identical digits (cids) the max3881 has a low phase and frequency drift in the absence of data transitions. as a result, long runs of consecutive zeros and ones can be tolerated while maintaining a ber of 1 x 10 -10 . the cid tolerance is tested using a 2 13 - 1 pseudorandom bit stream (prbs), substituting a long run of zeros to simulate the worst case. a cid tolerance of greater than 2,000 bits is typical. phase adjust the internal clock is aligned to the center of the data eye. for specific applications, this sampling position can be shifted using the phadj inputs to optimize ber performance. the phadj inputs operate with differen- tial input voltages up to ?.5v. a simple resistor-divider with a bypass capacitor is sufficient to set these levels (figure 4). when the phadj inputs are not used, they should be tied directly to v cc . system loopback the max3881 is designed to allow system loopback testing. the user can connect a serializer output (max3891) in a transceiver directly to the slbi+ and slbi- inputs of the max3881 for system diagnostics. to select the slbi inputs, apply a ttl logic high to the sis pin. interfacing with pecl input levels when interfacing with differential pecl input levels, it is important to attenuate the signal while still maintaining
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 8 _______________________________________________________________________________________ 50 ? termination (figure 5). ac-coupling is also required to maintain the input common-mode level. exposed-pad package the exposed-pad (ep), 64-pin tqfp incorporates fea- tures that provide a very low thermal-resistance path for heat removal from the ic. the pad is electrical ground on the max3881 and must be soldered to the circuit board for proper thermal and electrical performance. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled-impedance transmission lines to inter- face with the max3881 high-speed inputs and outputs. power-supply decoupling should be placed as close to v cc pins as possible. to reduce feedthrough, take care to isolate the input signals from the output signals. chip information transistor count: 2231 process: bipolar max3881 phadj+ (pin 5) phadj- (pin 6) 3.3v figure 4. phase-adjust resistor-divider max3881 50 ? 50 ? v cc 100 ? pecl levels sdi+ 25 ? 25 ? 0.1 f 0.1 f sdi- figure 5. interfacing with pecl input levels
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 9 max3866 max3881 pre/postamplifier overhead termination external termination required only if overhead circuit does not include internal input termination. this symbol represents a transmission line of characteristic impedance z 0 = 50 ?. v cc phadj- v cc lol gnd fil- fil+ sis ttl ttl sdi+ out+ v cc in+ fil out- lop ttl sdi- slbi- slbi+ system loopback phadj+ 0.01 f +3.3v +3.3v c f 1.0 f 124 ? pclk- +3.3v 84.5 ? 124 ? pclk+ +3.3v 84.5 ? 124 ? pd0 +3.3v 84.5 ? 124 ? pd15 +3.3v 84.5 ? typical application circuit
max3881 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 10 ______________________________________________________________________________________ package information 64l, tqfp.eps
package information (continued) +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery max3881 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products.
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max3881 part number table notes: see the max3881 quickview data sheet for further information on this product family or download the max3881 full data sheet (pdf, 240kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max3881ec b+d tqfp;64 pin;10x10x1mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e+3 * -40c to +85c rohs/lead-free: yes materials analysis max3881ec b+td tqfp;64 pin;10x10x1mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e+3 * -40c to +85c rohs/lead-free: yes materials analysis max3881ec b-d tqfp;64 pin;10x10x1 mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e-3 * -40c to +85c rohs/lead-free: no materials analysis max3881ec b-td tqfp;64 pin;10x10x1 mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e-3 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

▲Up To Search▲

Price & Availability of MAX3881ECBTD

	To Download MAX3881ECBTD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .